Soft IP Products To Increase Your Project Viability:-
1. Less circuit area for your project. Fit more on your chosen Intel Altera chip, or try for a cheaper (smaller or lower grade) chip.
2. Higher performance for software and bus master peripherals
3. Higher clock speeds
4. Easier place and route and timing sign off
5. Essential 'low cost' security capabilities, to satisfy government legislation and insurance requirements, and to protect your IP and your customers loyalty and safety
Failure to build in low cost, viable and readily available security solutions exposes developers, FPGA product makers and end users to government and insurance liability in the event of breaches and data theft! It also exposes your hard won project IP to theft and counterfeit. The fines and costs of recovery can FAR exceed the zero to very low hardware costs of adding security. Download the free '5 Essential Base-line Hardware Security Controls' brochure from ISDF16 below.
6. We bundle our IP together (and provide labs) to save you time, to fast track your project to better results.
LATEST INFORMATION ON THE EXCITING HYPERMAX DEVELOPMENT BOARD. HyperMAX is the ONLY HyperBus development board that supports Cypress HyperRAM and HyperFlash with an Intel FPGA. Exceptional hardware cost savings and performance gains are possible. This board employs Synaptic Labs HyperBus memory controller, the ONLY controller optimised for Intel FPGA. DOWNLOAD THE SHORT HyperMAX INFORMATION BROCHURE here . Excellent results for area constrained and IoT designs!
The exciting HyperMAX development board is available from Synaptic Labs partner, devboards GmbH. More information on the devboards website here .
2017 NEWS FLASH: EBV Elektronik (Avnet) selects Synaptic Labs' soft IP to win very significant gains in their exciting HyperMAX development board
GAINS WON by EBV Elektronik from Synaptic Labs' IP include ~55% higher clock speeds, more debug capabilities, up to ~1.8x faster software performance, and 20% less total SRAM, all while REDUCING the total Qsys project circuit area by 30%. We are constantly improving on these results. Read more here . Contact us to freely explore how Synaptic Labs' soft IP can transform your project.
2017 NEWS FLASH: EBV Elektronik (Avnet) selects Synaptic Labs' Cypress HyperRam and HyperFlash programmer and cache technology (CMS-T003). EBV won ~20% reduction in total circuit area for their exciting Intel Max10 / Cypress Hyper memories demonstration project on the latest DevBoards development board. Contact us for more information.
2017 NEWS FLASH: Synaptic Labs' tiny AES inline memory encryptor (SMEM-T001) that was included in our presentation at ISDF16 in Frankfurt is now available on the Intel Altera Design Cloud at this link . This simple lab demonstrates how easy it is to achieve secure boot and secure execution of code (XiP) from off-chip flash. This lab can be easily adapted for use with any COTS development board. See more information further below.
2017 NEWS FLASH: Synaptic Labs' advances a new controller for the exciting Cypress HyperRam and HyperFlash. Expect ~80% reduction in controller circuit area, no SRAM required, and far higher performance. It now costs LESS hardware resources to support HyperRAM and HyperFlash in FPGA than conventional DDR and EPCQ flash. Read more here . Contact us for more information about employing this extremely efficient HyperBus controller in your project.
2017 NEWS FLASH: Synaptic Labs' announces its new solution to achieve cryptographic authentication of firmware stored on EPCQ memory before the firmware is executed. The hardware cost of authentication is reduced from 64 to only 4 SROM. Contact us for more information.
2016 NEWS FLASH: Synaptic Labs' opened the hardware security session at Intel's annual event for partners and customers, ISDF16 in Frankfurt. Synaptic Labs' presentation focussed on the 5 ESSENTIAL (base-line) hardware security controls that are readily available today, at zero to very low hardware cost, for soft and hard (ARM) processor cores in FPGA devices.
These 5 essential hardware security controls specifically assist FPGA designers and corporations to satisfy the essential government and insurance requirements, to ensure a reasonable level of security is present, for example the German IT Security Act that requires compliance by 25 July 2017 at the latest.
Increase your project's SECURITY to also protect your investment in your project, and your customers loyalty. Also to be positioned to win a bigger share of the $Trillion that is expected to be spent globally on cybersecurity over the next 5 years.
DOWNLOAD Synaptic Labs' free ISDF16 2 page brochure on the FIVE ESSENTIAL HW SECURITY CONTROLS here. The more detailed and informative free slideshow presentation from ISDF16 can be accessed here . Synaptic Labs' presentation at Intel's ISDF16 (audio and slides), is also available from the Intel website here . Contact us for more information on adding essential security to your project with zero to very low hardware cost and high software performance.
SYNAPTIC LABS' PRODUCTS ARE AVAILABLE FOR FREE TRIALS NOW
All Synaptic Labs' COTS soft IP products are quick and easy to use. No special skills or tools are needed. Clear and easy tutorials are provided. You will quickly establish the benefits in your project with FREE trials.
Suitable for NEW DESIGN STARTS, LATE STAGE PROJECTS, AND RETRO-FITS.
Read more about what to expect Contact us to enquire, or for free trials, or customisation services
Product List, with more information further below:
- Inline AES encryptor (SMEM-T001) for off-chip flash (secure boot, secure XiP) that is a fraction of the circuit area of its nearest competitor.
- Cryptographic authentication of firmware on EPCQ flash for only 4 SROM in hardware cost. (Save 60 SROM.)
- Avalon interconnect (INTER-T002) to reduce interconnect circuit areas by up to 35% and increase interconnect clock speeds up to 40% - selected by EBV Elektronik (Avnet)
- Max10 onchip flash accelerator (CMS-T001) that is up to ~98% reduced circuit area and up to 630% faster software than the Altera accelerator
- A finer-grain SRAM allocation IP (SRAM-T001) that can save you up to almost 50% SRAM in a range of SRAM allocation sizes, plus up to 44% higher clock speeds, with up to 3.5x less circuit area consumed per SRAM allocation compared to the Altera SRAM allocation IP
- System caches / accelerators (CMS-T002/3) with non-burst to burst conversion from only 50 LE (approx 25 ALM) delivering up to 69x faster software and faster bus-master peripherals performance
- Tiny MMU and MPU that cost from only ~50 LE (~25 ALM) with 1 clock cycle CONSTANT timing
- All these capabilities can also be retro-fitted, to create a new generation for many deployed products and systems
- High performance Cypress HyperBus (HyperRam and HyperFlash) memory controller from only ~175 ALM (~350 LE) and zero to 2 SRAM, as selected by EBV Elektronik
- Nios II programmer IP for the Cypress HyperFlash as selected by EBV Elektronik
INVITATION TO ALL FPGA PROJECT DESIGNERS
CONTACT US with an indication of your list of requirements and objectives and OUR ENGINEERS who have more than 20 years experience WILL RESPOND to you with an indication of the circuit area reductions and other improvements (clock speeds, etc) you can expect to achieve when employing Synaptic Labs products. Projects targeting the smallest possible chip size may be able to reduce circuit area enough to use a smaller far cheaper chip. Projects targeting specific clock speeds and software performance may also be able to select a slower grade device, saving you up to 25% or more on your total chip purchase. In any case, Synaptic Labs' COTS soft IP products will also open up new options for your projects, by adding advanced capabilities or enhancements to existing Altera IP. This also means options that were previously dismissed as unsuitable can now be re-examined for viability.
To provide just one example out of many: Our System Accelerator (product CMS-T002/3) makes running software on the smallest Nios II/economy core more viable, for example by increasing software performance by up to: 69x on off-chip flash, 3.4x faster on SDRAM and 2.5x faster on on-chip flash in most Max10 devices and ALSO up to ~60x faster from on-chip flash in the smallest 2k Max10.
THE COMPARATIVE CIRCUIT AREA COST AND PERFORMANCE OF TWO REAL-WORLD PROJECT DESIGNS FOR SMALL ALTERA MAX 10 DEVICES
1. A TINY MICROPROCESSOR EMPLOYING THE NIOS II/ECONOMY CORE TARGETING THE SMALLEST 2K INTEL MAX 10 DEVICE. A complete 100 MHz NIOS II/e solution in only ~1630 LE and 8 KB SRAM for the smallest, cheapest ~2.3K LE, 12 KB, Intel Max10 FPGA (10M02). This design includes on-chip flash, I2C network and more. The Altera soft IP can ONLY deliver very slow software performance when executing code from the devices on-chip flash, and costs ~1.6k LE. Synaptic Labs' soft IP adds new capabilities - at an added cost of only ~200 LE - that: 1. Delivers up to ~60x FASTER software performance from on-chip flash in the 2k MAX 10 device, and 2. Enables the designer to easily and quickly allocate SRAM with very fine modularity across their design, whereas Altera IP is limited to coarse base-2 allocations. Fine grain SRAM allocation is critical in devices and projects with very limited SRAM resources, including the 2k MAX 10. The total circuit area cost of this enhanced project design still leaves ~500 LE of unused circuit area for the customer to place more of their own selected IP, because the tiny, low cost 2k MAX 10 device accepts 2.3k LE. NOTE: Synaptic Labs offers soft IP to transform the performance of the Nios II/e processor in all Altera device families, including delivering up to 69x FASTER SW performance from off-chip flash and 3.4x FASTER for SDRAM. This increases the viability of the Nios II/e generally, and also as a second (co-processor) in larger designs. Synaptic Labs' soft IP enables a Nios II system in practically all Intel PSG FPGA's. You can squeeze new $ value into existing designs without increasing FPGA size or speed grade, or try for a cheaper chip. Off-load interrupt processing to increase performance of other processor cores. Eliminate the cost of an external micro-processor from your designs bill of materials. Intel PSG customers can swap in Synaptic Labs HyperBus memory controller with HyperRAM and HyperFlash in LESS circuit area than it costs to implement the standard memory controller/s to support EPCQ memories. Intel Max10 projects also gain the benefit of XiP from high performance Cypress off-chip HyperFlash!
2. AN ALTERA MAX 10 NIOS II/FAST PROCESSOR PROJECT DESIGN IN UNDER 2k LE. Includes on-chip flash accelerator and some peripherals. Synaptic Labs' soft IP delivers up to 6.3x FASTER software performance compared to using the Altera soft IP (including the Altera flash accelerator). Synaptic Labs' project is always less circuit area (under 2k LE), while using Altera's far slower soft IP costs up to 1.4k LE more for the same design.
THESE ARE JUST TWO EXAMPLES. Tell us your target device and basic project requirements and we will estimate the benefits you will achieve by employing Synaptic Labs soft IP. Read more about the benefits in the Product List below. Request Free Trials to test results for yourself.
Synaptic Labs' products are important advances for complex or resource constrained projects of ANY size, and especially if targeting the Internet of Things. (Intel states it will manufacture 50 billion IoT devices by 2020.) These innovations have been created out of a multi-year R&D effort in collaboration with industry. Contact us for a free, no obligation discussion about how these soft IP products can enhance your project. Porting and other specialised services are available from our highly skilled and experienced (20+ years) FPGA design engineers.
All fully supported in QSYS and the Nios II development environment. QUICK LIST OF ALL PRODUCTS
SMEM-T001: A very small COTS AES Encryption Module for FPGA FLASH
Win more of the $Trillion that is expected to be spent globally on increased cybersecurity over the next 5 years. Easily INCREASE SECURITY in your project with this very small COTS inline AES ENCRYPTION MODULE that protects highly vulnerable FPGA FLASH. ITAR-Free. For soft and hard processors: the Altera Nios®II, ARM Cortex A (hard macro) and Cortex M (soft core), 8051 and other architectures. Tiny footprint: 210 ALM or 476 LE. Product Code SMEM-T001.
- Easy and quick to use COTS soft IP, fully supported in Qsys.
- No security skills, or specialist designer skills or tools, or external support required.
- Synaptic Labs' products can be combined to enable you to ADD this security while achieving BOTH:
1. FASTER system and software performance when using any of the ARM, Nios II/f and /e processors, and
2. COMPARABLE or even reduced TOTAL circuit area when using either the ARM or Nios II/f processors.
- Automatically encrypts data and code:
- at rest in the off-chip FLASH, and
- inflight to and from the soft or hard processors.
- Makes storage and execution of code and storage of client data in off-chip flash FAR safer.
- Protects your proprietary IP (against theft) and the device boot image in the FLASH
- Protects the safe operation of the device against unauthorised monitoring and low cost malicious re-programming.
"A cost effective solution any designer can use to protect your IP against easy reverse engineering and arbitrary reprogramming. Complements the bitstream protection and over-manufacturing protection capabilities found in modern Altera FPGA's, by protecting the otherwise fully exposed off-chip flash. For new projects, ongoing projects AND retro-fits.” Read the free White Paper championed by ex-NSA Technical Director Brian Snow on the need for better FPGA security.
FAR SUPERIOR AVALON INTERCONNECTS, FOR ALL ALTERA DEVICE FAMILIES. Reduces circuit area, increases interconnect clock speeds, and makes place-and-route and static timing sign off easier. Use with ARM hard and soft cores e.g. Nios II.
This COTS soft IP simply replaces certain Merlin Interconnect IP modules, for FAR superior results
"Simple and far superior replacements for the following functions of the Altera Qsys interconnect (aka the Merlin Interconnect) and Pipelined Bridges : 1-to-1 pipelined bridge logic - multi-bus master N-to-1 arbitration - multi-bus target 1-to-N address decoding, and - burst conversion logic"
- Burst capable instantiations will reduce interconnect circuit area by up to 36%.
- The critical path through the interconnect will easily exceed 150 MHz in low speed / lower grade Altera devices.
- Lower circuit area and higher clock speeds will make place-and-route of all Qsys projects easier.
- Lower memory access latencies measured in clock cycles and/or higher clock speeds for improved system performance and/or easier static timing sign off for your project.
- You retain full automated Qsys support for the entire range of Altera Protocol variants.
- You retain full automated support for bridging between Avalon and AXI Protocols.
- You can replace every occurrence of Altera's Avalon-MM interconnect in a SoC FPGA.
- FULLY SUPPORTED in Qsys and the Nios II development environment.
- Works with ARM hard cores, any type of soft processor core (e.g. Nios II/f and /e) and peripherals (co-processor, communications,..).
For new projects, ongoing projects AND retro-fits - Easy and quick to use - No specialist skills, no special tools needed.
The “Altera Merlin Interconnect” is composed of a large range of Qsys IP modules (see the Qsys IP Catalog / Qsys Interconnect / Memory-Mapped / …) that are instantiated automatically by Qsys. This includes the Avalon Protocol to Merlin Protocol translator, Merlin Burst Adapter IP, N-to-1 Arbitration of Merlin Masters and 1-to-N routing of memory transfer requests to Merlin Targets. This IP is automatically instantiated by Qsys on behalf of the developer in every Qsys project. Unfortunately, the circuit area of many Qsys projects is significantly increased by the Merlin Interconnect IP. Furthermore, the Merlin Interconnect IP frequently limits the top clock speed of a Qsys project. That all impacts on static timing sign off and place-and-route.
Our new COTS Qsys IP Interconnect modules provide a far superior solution, while retaining full automated Qsys support for the entire range of Altera Protocol variants. The final result will be a significantly lower circuit area solution, with support for lower memory access latencies and/or higher clock speeds and/or easier static sign off of your project. Our Qsys based solution will retain full automated support for bridging between Avalon and AXI protocols. SUITABLE FOR USE WITH ARM HARD AND SOFT PROCESSORS.
Our interconnect technologies are also currently being enhanced to deliver cache-coherent and real-time interconnects, as part of our Safe and Secure Real-time Project.
CMS-T001 - A FAR SUPERIOR, TINY SOFTWARE ACCELERATOR TO ALWAYS REPLACE THE ALTERA ON-CHIP FLASH ACCELERATOR IN EVERY MAX® 10 PROJECT
Fits in all Altera Max® 10 devices with a Nios II/fast processor, including in the smallest 2k devices: Product Code CMS-T001.
- Replaces ALL configurations of the Altera flash accelerator.
- SAVES up to almost 1400 LE. Requires only 35 LE and 1 SRAM.
- Up to 630% FASTER software performance on industry standard benchmarks.
- Faster boot times.
- Maintains optimal SRAM performance.
- Supports high Nios II clock speeds on the slowest grade Max® 10 devices.
- The Altera L1 instruction cache is always present to increase system performance by performing all normal caching functions for all memories (e.g. SDRAM, on-chip flash) and bus-master peripherals. The Altera flash accelerator disables the Altera L1 instruction cache. This has undocumented negative impacts, including disabling of all cache-line pre-fetch capabilities over the instruction_master port. That drops Nios II/f performance a lot. CMS-T001 has none of those problems.
- Supports cache storage capabilities from 64-bytes (for measurements based real-time applications) up-to 64-Kilobytes (for maximum general purpose performance)
For new projects, ongoing projects AND retro-fits - Easy and quick to use: No specialist skills, no special tools needed.
SRAM-T001. SUPERIOR SRAM ALLOCATION FOR EVERY ALTERA PROJECT, IN ALL ALTERA DEVICE FAMILIES
This COTS soft IP simply replaces the coarse-grain Altera on-chip memory IP. An essential tool especially in low cost devices.
"Global cyber security expenditure is reported to reach a $Trillion over the next 5 years"
Synaptic Labs products will help Altera developers to win a greater share by enabling higher security - often with higher performance.
- Automatic, finer-grain, memory allocation for all Altera devices in Qsys. Highly configurable. You can SAVE precious SRAM (M9K, M10K, M20K) resources in many SRAM instantiations.
- Simplifies and accelerates distribution and comparative testing of different SRAM allocation sizes, so you can choose the BEST options.
- Easily adjust SRAM allocation sizes with finer granularity as your design needs change.
- Includes an integrated burst converter and finer grain pipeline controls that deliver up to 44% faster clock speeds, in up to 3.5x LESS circuit area i.e. reduces your total circuit area and makes place and route easier.
- FULLY SUPPORTED in Qsys and the Nios II development environment.
- Works with ARM hard cores, any type of soft processor core (e.g. Nios II/f and /e) and peripherals (co-processor, communications,..) with bus-master capabilities.
For new projects, ongoing projects AND retro-fits - Easy and quick to use - No specialist skills and no special tools are needed.
When allocating SRAM with SRAM-T001 you will quickly and efficiently:
- Achieve typically 5% to 30% faster clock speeds for NON-BURST mode; and
- Achieve typically 20% to 44% faster clock speeds for BURST mode. Helps make place and route easier.
- Reduce total circuit area by ~64 ALM (~128 LE) for EACH bus master port of the Nios II/fast core that has burst mode enabled.
- Eliminate the up to almost ~50% SRAM waste that can be caused by the Altera SRAM IP. Altera “On-Chip SRAM” IP only allocates SRAM in BASE 2 (i.e. coarse-grain: 1, 2, 4, 8, 16, 32, 64 KB, …) with a limited range of non-base 2 options. For example, if you request 17 KB, Altera SRAM IP will allocate 32 KB. SRAM-T001 simply allocates 17 KB. You save 15 SRAM.
- Simplifies and accelerates the distribution, testing and best selection of SRAM design choices. Quickly apply different size SRAM allocations to different targets, and then test and compare the results. Select the BEST options. Easily adjust SRAM allocations as your design requirements shift, thanks to SRAM-T001's finer granularity and superior pipelining controls.
- Highly configurable. Finer-grain distribution of all valuable SRAM resources in the sizes you want, where you want, to achieve the BEST results for YOUR project.
- Removes the need for every project to try to work around the Altera SRAM allocation limitations. It removes the problems and inefficiencies that other work-arounds introduce. For example, trying to instantiate the Altera “On-Chip SRAM” IP twice (for use as a single contiguous region of memory) costs extra time, effort, extra circuit area and can result in slower clock speeds and wasted memory. That type of workaround is not automatically supported in the Nios II development tools. That leads to frustration as the inefficiencies are introduced. SRAM-T001 simply removes all those problems, and enables you to quickly and efficiently select and test more specific SRAM allocation sizes, where you want, when you want, for the BEST results.
- Plus win the other benefits listed above, such as faster clock speeds for simplified place and route and total circuit area savings.
All soft IP modules are 'universal', and suitable for most Altera device families (unless specifically noted). All modules are highly viable for NEW projects and open the door for exciting RETRO-FIT opportunities, because of low licence fees and low chip resource demands . Licences from less than $1k.
SOME SELECTED USE CASES AND VALUE PROPOSITIONS ARE PROVIDED BELOW: