QUICK LIST OF PRODUCTS
Easy to use soft IP modules and tools that are all FULLY supported in Qsys for SUPERIOR RESULTS
1. AES INLINE ENCRYPTION FOR HIGH RISK OFF-CHIP FLASH
A simple, easy to use, very cheap, low circuit area, security solution to encrypt data and code that is: A) at rest in the off-chip FLASH, and B) inflight to and from the soft or hard processors. Makes storage and execution of code from large cheap off-chip flash, and storage of client data in flash, FAR safer. Protects your proprietary IP and customer data in the FLASH, as well as the safe operation of the device against malicious re-programming. Combine with products 2 or 3 and achieve encryption security with FASTER software performance!
2. TINY MULTI-USE SYSTEM CACHE MODULE (CMS-T003)
Employ to accelerate software or a bus-master peripheral, and/ or as a 'non-burst to burst' convertor. Requires only 50 to 100 LE.
A tiny 2-way set associative SYSTEM cache for use with the Nios II/e or a bus-master peripheral when accessing flash or SDRAM, to VERY strongly accelerate (E.G. UP TO 69x) software performance. Makes storage and execution of code from large cheap off-chip flash FAR more viable. Can also be employed as an Avalon non burst to burst converter to accelerate flash or SDRAM access. Also an ideal replacement for Altera’s Nios II/f flash accelerator for Cyclone, Arria and Stratix projects, for far superior results.
3. VERY SMALL MULTI-USE SYSTEM CACHE MODULE (CMS-T002)
Employ to accelerate software or multiple bus-master peripherals. Requires from only 276 LE.
A very small fully-associative SYSTEM cache for use as a L1 cache for Nios II/e or as a L2 cache for Nios II/f. Cache multiple bus-master peripherals. Suitable for flash or SDRAM. Makes storage and execution of code from large cheap off-chip flash FAR more viable. Also an ideal replacement for Altera’s Nios II/f flash accelerator for Cyclone, Arria and Stratix projects, for far superior results. Also gives better results for programs like Linux, and less worse case behaviour.
4. ON-CHIP FLASH ACCELERATOR (CMS-T001)
Easily replaces the Altera Nios II/f flash accelerator on all Altera MAX 10 FPGA to achieve up to 4x faster performance with the lowest combinatorial logic overhead. Requires only 35 LE.
5. SRAM MODULE WITH INBUILT BURST CONVERTER (SRAM-T001)
Easily enables highly granular, high-clock speed, on-chip memory instantiation in Qsys. Can save up to 50% of SRAM (M9K, M10K, M20K) resources in every instantiation, up to 44% higher clock speeds and up to 3.5x less circuit area when compared to using Altera’s on-chip memory IP.
6. AVALON INTERCONNECT SOLUTIONS (coming soon)
Easily reduce circuit area and win higher clock speeds with these Altera Avalon protocol interconnect technologies. For use with Qsys in general purpose applications.
7. TINY MMU/MPU SOLUTIONS (coming soon)
Highly innovative, high-performance, tiny circuit area, MMU/MPU's (e.g. ~50 LE with 1 clock cycle CONSTANT timing). Suitable for Nios II/economy, Nios II/fast and bus master peripherals.
ALL PRODUCTS ARE FULLY SUPPORTED IN QSYS, and COME WITH STEP BY STEP TUTORIALS. NO SPECIAL FPGA DESIGNER SKILLS OR TOOLS ARE NEEDED. Request Free Trials in the blue CONTACT tab above.
All these products form part of a multi-year R&D effort to create highly innovative HIGH PERFORMANCE safety critical and mixed-criticality solutions that can be easily exploited in both FPGA and/or ASIC.