Product CMS-T002/3 - Reusable System Caches (System Accelerators) with Non-Burst to Burst Converter
Best-in-class solutions in ONE PRODUCT, for lowest circuit area and highest performance. Employ to accelerate software or bus-master peripherals access to SDRAM, on-chip flash and off-chip flash, and/ or as a 'non-burst to burst' convertor to save 4x less circuit area compared to using Qsys IP. Requires from only 50 LUT.
Two highly configurable System Caches (System Accelerators) are included in our CMS-T002/3 product. Their tiny footprint means you can use one or both caches in your design, or use them multiple times throughout your design, matching the best System Cache to each need, to maximise the benefits.
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QUICK SUMMARY: Highly configurable to suit any project. Select between tiny 2-way set associative up to 16-way fully associative SYSTEM caches with TRUE LRU eviction. For use with soft processors (e.g. Nios II/FAST and the smallest Nios II/Economy cores) AND bus-master peripherals (with or without a core being present) when accessing on-chip and off-chip flash and SDRAM, to VERY strongly accelerate (e.g. UP TO 69x faster on the smallest Nios II/Economy core) software performance. Makes storage and execution of code from SDRAM and especially large cheap off-chip flash FAR more viable. Can also be employed as an Avalon non burst to burst converter to accelerate flash or SDRAM access. This will benefit various processors and bus-master peripherals that operate in 'pipelined non-burst' or 'pipelined burst of 1' mode. Can REDUCE total circuit area in your design when used for burst conversion compared to using Qsys IP (requires 4x LESS circuit area - using our IP for burst conversion will REDUCE your TOTAL circuit area). Also an ideal replacement for Altera’s Nios II/f flash accelerator for Cyclone, Arria and Stratix projects, for far superior results.
For example, when used as a system accelerator @150 MHz for the Nios II/ECONOMY core:
Delivers SOFTWARE PERFORMANCE that is up to 3.4x FASTER on SDRAM, 69x FASTER on OFF-chip flash (yes, up to 69x) and 2.5x FASTER on ON-chip flash. This makes large, cheap, off-chip flash a more viable option for running code in many Altera device sizes and families (including in the Max®10 range). Designs that already exploit the small Nios II/e processor can now free up valuable SRAM by viably storing and executing far more code in large, very cheap off-chip flash.
This SOFTWARE ACCELERATION delivered by the TINY CMS-T003 System Cache makes the small Nios® II/ECONOMY core a much more viable option:
- in the smallest Altera devices, and
- as an EXTRA core in larger devices, for running some code separately (for example in large, cheap off-chip flash).
For example, when used as a burst converter for the Nios II/FAST core:
When the Nios II/f data cache is operated in burst mode, the Altera Merlin Interconnect automatically introduces a 'pipelined burst of 8 to pipelined burst of 1' converter. This costs ~ 112 ALM (i.e. ~ 224 LE). However, Altera documentation recommends operating the Nios II/f data cache in non-burst mode, for best results when accessing SRAM and peripherals. In this case, our System Cache / accelerator CMS-T003 can be employed as a 1 Kilobyte 2-way set associative L2 cache to win two advantages. Firstly, it will operate as a 'pipelined read burst of 1 to burst of N converter', to win superior read performance when accessing flash and SDRAM. Secondly, it will simultaneously reduce the number of conflict misses from the Nios II/f L1 cache. In other words, CMS-T003 when employed as a burst converter and system cache, allows you to win the best performance results for all memory types, and less conflict misses generally. In this example CMS-T003 costs only 30 ALM (i.e. 60 LE) and 1KB of RAM. That is almost 4x LESS circuit area than when employing the Nios II/f data cache in burst mode. Plus you win the other advantages.
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CMS-T003 FEATURES AND BENEFITS - A High Performance Write Through System Cache. For all memories when using the Nios® II/ECONOMY PROCESSOR in all ALTERA Families. Also Accelerates BUS-MASTER PERIPHERAL access to Memories, with or without a Processor Core. Also a burst converter that means you can employ the CMS-T003 IP and REDUCE the total circuit area in your design.
- Tiny circuit area that fits in the smallest devices, including new Max® 10 2K range devices
- Delivers up to 69 times faster software performance when software is running directly(XIP) from serial flash (SPI)
- For On-chip flash, Off-Chip flash and SDRAM memories
- Improves the viability and value of running software directly from FLASH or DDR
- Delivers faster boot times
- Time analysable
- Ideal for low power applications
- Maintains optimal SRAM performance
- Configurable across various performance/area tradeoffs
- Up to 2 way set-associative cache with true LRU eviction behaviour
- No modification to existing software
- Easy to upgrade existing Nios® II Qsys projects
- Supports high Nios® II clock speed on the slowest-grade Altera Max® 10 devices
- Simple to use: No specialist skills or tools needed
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Accelerators (CMS-T001, CMS-T002, CMS-T003) that can easily replace the Altera ON-CHIP FLASH accelerator in less circuit area, while also adding more capabilities. For example, our tiny CMS-T001 on-chip flash accelerator delivers up to 620% FASTER software performance in up to 43x (yes, up to 43 times) LESS circuit area than the Altera accelerator. Circuit area savings can FAR exceed the area cost of using our IP.
2. FOR ALL DEVICE FAMILIES: The burst conversion logic in our very small SRAM instantiation IP (SRAM-T001) enables you to save up to 3.5x LESS circuit area EVERY TIME Qsys would currently employ the Merlin Interconnect for burst conversion (i.e. in all cases where burst length is >1 e.g. with the Nios II/f core, etc). Using our SRAM product not only gives you far superior granularity over Qsys SRAM allocation, it also enables you to save circuit area every time it is used throughout your design. The total circuit area in your design goes down, and higher clock speeds are easier to achieve in QUARTUS and across your entire design. The burst converter logic also delivers ~15% higher performance than when using the Qsys IP. So using SRAM-T001 is all Win/Win/Win. The more you use our SDRAM-T001 product in your design, the more your circuit area and design effort costs diminish, over using the Qsys SRAM IP. Circuit area savings can FAR exceed the area cost of using our IP.
3. FOR ALL DEVICE FAMILIES: The burst conversion logic in our tiny System Cache / accelerator CMS-T003 delivers better results in %) LE than when using the Nios II/f data cache in burst mode which costs ~220 LE. That is almost 4x LESS circuit area. You reduce total circuit area in your design when adding our IP. Read more details in the CMS-T003 product description accordion above. Circuit area savings can FAR exceed the area cost of using our IP.
ALL OUR IP IS FULLY COMPATIBLE WITH QSYS AND THE NIOS II DEVELOPMENT ENVIRONMENT.
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