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Saturday, August 27, 2016


altera max 10 fpga 2AVAILABLE FOR FREE TRIALS NOW

FOR NEW DESIGN STARTS, LATE STAGE PROJECTS, AND RETRO-FITS IN DEPLOYED PRODUCTS AND SYSTEMS. You can EASILY achieve better results, new capabilities, smoother design flowsreduce circuit area in your design, and much more.  Read more about what to expect Also contact us for customization services.


These innovations have been created out of a multi-year R&D effort in collaboration with industry and Altera (now the INTEL Programmable Solutions Group).  To arrange Free Trials, contact your INTEL PSG 'Altera' sales representative or field application engineer, or simply use the Contact form QUICK LIST OF ALL PRODUCTS


Product List - All fully supported in QSYS and the Nios II development environment 

All soft IP modules are 'universal', and suitable for most Altera device families (unless specifically noted).  All modules are highly viable for NEW projects and open the door for exciting RETRO-FIT opportunities, because of low licence fees and low chip resource demands . Licences from less than $1k.

Enquire or Request Free Trial

ALL PRODUCTS AND SOME KEY FEATURES ARE PRESENTED IN THE ACCORDIONS ABOVE.  SOME SELECTED USE CASES AND VALUE PROPOSITIONS ARE PROVIDED BELOW:

 


Risk auditors and security managers:

Today there can be no excuse for not including FPGA devices in your security risk audits, or for failing to employ the free to low cost AES protection that is readily available for many FPGA devices.  

"Programmable (FPGA) devices are designed to be monitored and re-programmed in the field.  This makes them a logical target for hacking.  Every FPGA should be deployed with a base-line of encryption security, in the same way that desktops, mobile devices and even $1 online transactions are protected. Synaptic Labs' AES product protects the most exposed low cost attack vector in most FPGA's i.e. data and code at rest, and in flight to and from, the off-chip flash.  Use this product to achieve a base-line of security, to protect what is currently a weak link in many commercial and industrial security chains."  Brian Snow former Technical Director, United States NSA.

Every FPGA with off-chip flash should use encryption to deliver a base-line of protection to this highly vulnerable attack vector in FPGA's, to protect the FPGA itself, and to strengthen your corporate security chain.

 

SIMPLIFYING DESIGN FLOWS

These products are designed to simplify design flows, to make your work easier and less complicated. Some examples:
Our SRAM allocation tool (SRAM-T001) overcomes the problem of Qsys coarse grain SRAM allocation, can save you SRAM, plus can reduce circuit area up to 3.5x and increase clock speeds up to 44% over using burst conversion logic generated by Qsys. Win/Win/Win. Our System caches (CMS-T002/3) also include integrated bus-master arbitration logic that also reduce circuit area and give higher clock speed results than relying on bus-master arbitration generated by Qsys.  All very important in area constrained and / or larger complex projects.  Also accelerate bus-master peripheral's access to memories.  Also, software acceleration can make the smallest Nios II (Economy) core far more viable in the cheapest, lowest resource Altera devices, or in larger devices that can benefit from including a small processor for running some tasks separately.  Acceleration can make large, cheap off-chip memories far more viable in your project (especially when using the Nios II/Economy core), to increase memory and software capacities at very low cost. Our AES product can protect your IP and customer loyalty (SMEM-T001).  Use our risk free, Free Trials to evaluate the benefits in your own projects.

 
EASILY ACHIEVE MORE IN YOUR PROJECTS
  • Increase software and bus-master peripherals performance
  • Reduce design complexity and effort
  • Save time and money
  • Add more security to protect your IP, customer loyalty, safety
  • Save SRAM
  • Save circuit area
  • ..... and more
 
"These products will make many design projects easier and more commercially viable."  

 
NEWS FLASH
SYNAPTIC LABS AND BRIAN SNOW COMPLETE WHITE PAPER ON THE NEED FOR BETTER SECURITY IN COMMERCIAL FPGA DEVICES AND FPGA SECURITY RISK ASSESSMENTS. This helpful publication for FPGA designers and security risk assessment auditors can be download for FREE here .     

"It will be ALWAYS be helpful to have these solutions in your designers tool kit
To assist you to explore NEW design and configuration OPTIONS and ENHANCEMENTS 
To easily IMPROVE your new projects and SIMPLIFY implementation
 To UPGRADE your existing products (retro-fit)
Solutions that help YOU to create
BETTER products for a BRIGHTER future"


Chip designers:  Learn more about about What To Expect when using these products here

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