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Synaptic Laboratories HyperBus Memory Controller - One highly efficient module for both HyperRAM and HyperFlash
Up to 10x smaller in circuit area than the HyperBus memory controller offered by Cypress itself, and greatly reduced SRAM 
Also a HyperFlash Programmer that supports Nios II project development with no hardware cost

Contact us for a no obligation free discussion with our senior design engineers about how your project can benefit from this IP!

You can also REQUEST A MEETING WITH SYNAPTIC LABS before, during or immediately after EMBEDDED WORLD in NUREMBERG 14 - 16 MARCH, 2017. (Available for no obligation discussions from 11th to 18th inclusive.)

   Enquire or Request Free Trial

  • S/Labs' Superior HyperBus Memory Controller for HyperRAM and HyperFlash

    Requires very small circuit area and optionally 0 or 1 SRAM.  Current version is ~84% smaller than the Cypress HyperBus controller:
       Under~275 Adaptive Logic Modules with 1 SRAM { equiv. to ~550 4-to-1 Logic Elements (LE) }
       Under ~390 ALM with 0 SRAM { equiv. to 780 LE }
       Currently being reduced to under ~175 ALM (350 LE) 
    Delivering 140MHz -  and currently being upgraded to ~ 200MHz
    ENABLING HIGH PERFORMANCE HYPERBUS SOLUTIONS IN CHEAPER SIZE CHIPS AND SPEED GRADES
    Intel PSG customers can swap in HyperRAM and HyperFlash in LESS circuit area than it costs to implement the standard memory controller/s to support EPCQ memories. 
Selected by EBV Elektronik (Avnet) for use in their HyperMAX development board demonstrations and workshops.  

Register for an EBV HyperMAX workshop at Embedded World 2017 here .  Or ask your EBV (Avnet) representative to arrange a demonstration.  See Synaptic Labs' IP at work!
TWO USE CASE EXAMPLES BELOW
1. EBV ELEKTRONIK (AVNET) HYPERMAX PROJECT
2. A TINY MICROCONTROLLER FOR ALL INTEL PSG FPGA - INCLUDING THE SMALLEST CHEAPEST 2K INTEL  MAX10


1.  USE CASE EXAMPLE:
S/LABS' SOFT IP DELIVERS STRONG 
REAL WORLD BENEFITS IN THE EBV ELEKTRONIK (AVNET) HYPERMAX DEMONSTRATORS
EBV Elektronik's entire project previously could only fit in a 16k size device.  After employing S/Labs' soft IP, the entire project now fits very comfortably, with resources to spare, in a far cheaper 8k size device, while still achieving up to ~76% higher performance. 

The original project employed the standard Cypress HyperBus memory controller:

  Total circuit area:  ~10,250 4-to-1 LE (Intel Max10 measurements)
  Total SRAM required:  94 SRAM (including the 18 SRAM required for the standard Cypress HyperBus controller)
  Lab system performance:  75 MHz

THE DESIGNERS FLEXIBILITY, AND THE BENEFITS IN YOUR PROJECT, INCREASE SEQUENTIALLY AS MORE S/LABS' IP IS EMPLOYED.  
FOR EXAMPLE, IN THE EBV ELEKRONIK (AVNET) PROJECT: 

 1. AFTER SWAPPING IN S/Labs' HyperBus memory controller IP:
  Total circuit area reduced to:   7,228 LE (and can be lower)  
  Total SRAM reduced to:       76 SRAM
  Lab system performance increased to:  110 MHz
 2. AFTER ADDING IN S/LABS' Avalon interconnect IP:
  Total circuit area:   6,194 LE
  Total SRAM required:  76 ( 0 extra )
  Lab performance:   115 MHz
 3. AFTER employing S/LABS' SRAM allocator IP to increase MHz:
  Lab system performance increased to:  125 MHz
 
PROJECT GAINS AVAILABLE:
Total circuit area REDUCED up to 42%
  From ~10,250 down to 6,194 LE - and could already be reduced further, down to 5,767 at cost of 1 extra (77 total) SRAM
Total SRAM REDUCED by ~20% 
  From 94 down to 76 (or 77)
Total system performance can be INCREASED up to ~76%
  From 75 MHz to 125 MHz

These increases in performance are the equivalent of stepping up in chip size or speed grades (without the added chip costs).

The reductions in circuit area and SRAM make projects much more viable in smaller or slower speed grade, lower cost, FPGA chips.  The perfect result!   
 

THESE ABOVE RESULTS WILL BE IMPROVED, AS THE PERFORMANCE OF S/LABS' HYPERBUS MEMORY CONTROLLER IS CURRENTLY ON AN ENHANCEMENT PATHWAY TO DELIVER ~200 MHz 

The more S/Labs’ IP is employed, and the more complex the project, or the more resource constrained, then the more valuable flexibility our IP can deliver to the designer.

You can win better results, with easier place and route, and faster project sign off:

   • More circuit area reductions, and/or

   • Higher clock speeds, and/or

   • Fit more logic and functionality into your chosen FPGA device, while still satisfying your project's static timing requirements

Or try for a cheaper chip size or speed grade, to save significant costs for your entire project.


2.  USE CASE EXAMPLE: 
A TINY MICROCONTROLLER FOR ALL INTEL PSG FPGA'S (even the smallest 2k Max10)

Thanks to S/Labs' IP, it CAN now require LESS circuit area to implement HyperBus with HyperRAM and HyperFlash than to implement standard controller and memories. Perfect for smallest FPGA and resource constrained projects!

A complete 100 MHz NIOS II/e solution in only ~1630 LE and 8 KB SRAM when using standard memories
Requires only ~1500 LE and 9 SRAM when swapping in the far superior S/Labs' HyperBus memory controller with HyperRAM and HyperFlash
HyperBus also permits XiP from off-chip flash, which is NOT supported on Intel Max10 with standard memories.

A tiny microcontroller e.g. for the smallest, cheapest ~2.3K LE, 12 KB, Intel MAX 10® FPGA (10M02)

• Uses the smallest Nios® II economy core @ 100 MHz

• Uses S/Labs’ SRAM allocation IP to allocate exactly 3KB on-chip SRAM

• Uses S/Labs’ Avalon interconnect IP to reduce circuit area and increase clock speeds

• Uses S/Labs’ tiny 2-way set-associative cache IP @ 100 MHz

Delivers ~60x FASTER software performance from Altera on-chip flash @ 7.5 MHz (up to 69x FASTER from off-chip EPCS flash memory)

• Employs a I2C network interface for controlling external peripherals

• ~670 LE and 4 KB remains available to the user

To create custom logic to control I/O pins of this tiny 10M02 MAX 10


SWAP IN S/Labs' HyperBus memory controller for HyperRAM and HyperFlash to win the ADVANTAGES of the Cypress memories (including XiP from high performance off-chip Cypress HyperFlash) while REDUCING total circuit area. WIN/WIN/WIN

S/Labs' soft IP enables a Nios II microcontroller system in practically all Intel PSG FPGA products

• Achieve more in cheaper (smaller, lower speed grade) FPGA's OR squeeze new $ value (new functionality, higher performance) into existing designs without increasing FPGA device size or speed grade

• Off-load interrupt processing to increase performance of other processor cores

• Eliminate the cost of an external micro-controller from a design’s bill of materials


AN EXAMPLE BLOCK DIAGRAM FOR THE SYNAPTIC LABS' HYPERBUS MEMORY CONTROLLER for Intel FPGA 

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